In a memory architecture, a bit line is coupled with a plurality of memory cells. Each of the memory cells has some leakage current when a pass gate transistor in the memory cell is turned off, and draws a larger current value when the pass gate transistor is turned on. For illustration, the leakage current when the pass gate transistor is turned off is called current Ioff while the current drawn by the memory cell when the pass gate transistor is turned on is called current Ion. The number of memory cells that can be coupled with a bit line depends on a ratio of current Ion of an accessed memory cell over currents Ioff of un-accessed memory cells. For example, as the ratio increases, a number of memory cells coupled with the bit line increases. The memory density of the memory architecture is higher for a larger ratio. In contrast, when the ratio is smaller, the number of memory cells capable of being coupled with the bit line is reduced, which reduces the memory density. Effectively, current Ioff of each memory cell and the ratio based on Ion and Ioff effects the density of the memory architecture.
Like reference symbols in the various drawings indicate like elements.